In prior art applications, such as generally shown in FIG. 1, the typical current or voltage regulator 10 includes regulator control circuit 12 and a control loop or feedback network 14 for regulating the output 22 provided to the load 16. The voltage output of the regulator 10 is usually set by a reference signal (current or voltage) SREF indicated at 18, while the output of the regulator 10 is typically bypassed with a single large capacitor 20. When the desired output voltage VOUT is required to change by a significant amount, the large output capacitor 20 must be charged or discharged to achieve the new regulation voltage VOUT. This causes the transition time between regulated states to be excessively long and impractical for applications where the transition times must be less than several micro seconds. The large output capacitor 20 thus directly limits the step-response of the regulator's control loop.
More specifically, in order to change the regulation state of the regulator, the reference signal SREF is changed at the input 18. When the reference signal SREF is changed, the slew-rate of the output Vout at 22 is limited to the current sinking or sourcing capabilities of the regulator 12, the impedance of the load 16, the size of the output capacitor 20, and the bandwidth of the regulator's control loop 14. For a stable control loop, the rise-time or decay time of the output may be limited from tens to hundreds of microseconds. This may be acceptable for systems where a single regulation state is desired, but can be unacceptable where the regulator is designed to operate in any one of a plurality of regulation states. It is desirable to provide a solution to allow a very fast response time to change from one regulation state to another without redesigning the control-loop, changing the bandwidth of the control-loop, or reducing the size of the output capacitor.